1. Field of the Invention
The present invention relates to a multiple clock domain logic system, and more particularly, to a system and method for performing scan tests with a single scan clock.
2. Description of the Prior Art
Digital logic circuits are commonly applied in many electronic devices. A digital logic circuit includes combinational circuits and sequential circuits. The combinational circuits generate output signals according to current input signals. The sequential circuits, which have memory functionality, can generate output signals according to previous input signals along the time axis.
Devices for circuit debugging and testing are usually required when designing and producing a digital logic circuit. Circuit testing devices in the art include a plurality of flip flop scan cells (as shown in FIG. 1) linked together to form a scan chain (such as the scan chain 200 shown in FIG. 2). Loading predetermined logic values into a scan chain to debug a digital logic circuit is known as a scan test.
Please refer to FIG. 1 showing a block diagram of a D-type flip flop scan cell 100 in the prior art. The D-type flip flop scan cell 100 comprises a D-type flip flop 102 and a multiplexer 104 for selectively outputting a function input signal D or a scan input signal SI according to a scan enable signal SE. When the scan enable signal SE is in a scan enable state, the multiplexer output end 138 sends the scan input signal SI to the D-type flip flop 102. When the scan enable signal SE is in a scan disable state, the multiplexer output end 138 sends the function input signal D to the D-type flip flop 102. The D-type flip flop 102 outputs a corresponding output signal through an output end 116 according to the inputted signal received from the multiplexer 104 or outputs a corresponding complementary output signal through a complementary output end 118 according to the inputted signal received from the multiplexer 104. Please refer to FIG. 2 showing a scan chain 200 in the prior art. A plurality of D-type flip flop scan cells 210, 230 is linked together to form a scan chain 200. A scan input end 234 of the next D-type flip flop scan cell 230 is electrically connected with a data output end 220 of the previous D-type flip flop scan cell 210 to form the scan chain 200. When the scan enable signal is in a scan enable state, the scan input signal is inputted into the scan chain 200 sequentially according to a clock signal Clk. The goal in providing the sequential circuits, such as the D-type flip flop scan cells 210, 230, with predetermined logic values respectively to debug the logic system is accomplished.
Some logic systems need at least two clock signals for synchronization. The combination of devices operating according to the same clock signal is defined as a clock domain. Accordingly, a logic system of this kind includes at least two clock domains. The devices of each clock domain operate according to the clock signal of a specific frequency corresponding to the clock domain.
A multiple clock domain logic system 500 is shown in FIG. 3. The D-type flip flop scan cells 512, 514, 516, 522, 524, 532 of the logic system 500 rely on the clock signals of different frequencies as the base for synchronization so that the scan cells 512, 514, 516, 522, 524, 532 belong to the different clock domains 510, 520, 530. Hence when the multiple clock domain logic system 500 of the prior art is performing a scan test, the clock domains 510, 520, 530 receive the scan input signals scan_in_1, scan_in_2, scan_in_3 respectively to perform the scan test and output the scan output signals scan_out_1, scan_out_2, scan_out_3 respectively. Please refer to FIG. 4. Corresponding to the number of the scan input signals scan_in_1, scan_in_2, scan_in_3 and the scan output signals scan_out_1, scan_out_2, scan_out_3, a scan test equipment should include enough number of input ports and output ports for performing the scan test. However, the price of the scan test equipment corresponds to the amount of scan input signals scan_in_1, scan_in_2, scan_in_3 and scan output signals scan_out_1, scan_out_2, scan_out_3. Furthermore, while loading a shorter scan chain with one of the scan signals is completed during a scan test, only a part of loading a longer scan chain with one of the scan signals is completed so that the input ports and the output ports corresponding to the shorter scan chain are idling and waiting for the full completion of loading the longer scan chain. As a result, the scan test equipment is not fully utilized while shortening the time for the scan test is impossible.
Known in the art, a conventional apparatus for linking the scan chains of different clock domains with latches is shown in FIG. 5. The elements of FIG. 5 correspond to the elements of FIG. 3 while the scan chains of different clock domains are linked with D latches 702, 704. However, all clock signals clk1, clk2, clk3 should be provided for performing the scan test of the multiple clock domain logic system 700, and the arrangement of the scan chains in FIG. 5 should be first linking the D-type flip flop scan cells of the same clock domain and second linking the clock domains according to the order of the frequencies of the clock signals of the clock domains; rather than first adjusting the amount of the scan chains according to the amount of input ports and output ports and second equalizing the lengths of the scan chains to load the scan chains in parallel to solve the problem of the idling status of the input ports and the output ports. As a result, the known in the art apparatus of linking the scan chains of different clock domains with latches is not a solution of the above-mentioned problem.